The present invention generally relates to a method and/or architecture for implementing an output buffer, and more particularly, to a method and/or architecture for implementing a high speed output buffer with ON resistance and skew control.
Conventional approaches for implementing output buffers use a pre-buffer section to control rise and fall rates of gate voltages. Referring to FIG. 1, a schematic of a circuit illustrating such an approach is shown. The circuit 10 comprises a pre-buffer 12 and an I/O circuit 14. The pre-buffer 10 comprises a current source I1, a current source I2, a number of MOSFETs P1-P8 and a number ofMOSFETs N1-N8. The circuit 10 receives the signal IN. The circuit 10 generates the signal OUT1 and the signal OUT2. A current on the signals OUT1 and OUT2 (presented, for example, to output capacitors C1 and C2) has the relationship i=cdv/dt. By limiting the transient current of the signals OUT1 and OUT2, by controlling a turn on rate of the MOSFETs P7, N7, P8 and N8, the likelihood of rapid rates of change of current in the power and ground inductances is reduced. In turn, a ground or power bounce voltage via the relationship v=ldi/dt is reduced. The pre-buffer section 12 also causes the output device P7 connected to the output OUT1 to shut off before the MOSFET N7 turns on, limiting crowbar current in the MOSFET P7 and the MOSFET N7. The pre-buffer 12 operates as follows: (i) if the MOSFET P7 is on and the MOSFET N7 is off, then the MOSFET N3, the MOSFET N4 and the MOSFET N5 are on, while the MOSFET P2 remains off; (ii) if the signal IN goes high, the MOSFET N3 and the MOSFET N5 turn off immediately, while the MOSFET P2 turns on fast and the MOSFET P7 shuts off fast. At the same time, the MOSFET N6 turns off fast and the MOSFET P6 begins to pull the gates of the MOSFET N8 and N7 high. The gates of the MOSFET N7 and N8 are pulled high slowly, since the MOSFET P6 is a weak MOSFET.
The weak MOSFET P6 is also assisted by the current source I2 and a current mirror (i.e., the MOSFET P3, the MOSFET P4, and the MOSFET P5). When the weak MOSFET P6 is assisted by the current mirror, the MOSFET P7 and the MOSFET P8 turn off fast, while the MOSFET N7 and the MOSFET N8 turn on slowly. The MOSFET N7, the MOSFET N8 turn off fast in the opposite direction with the MOSFET P7 and the MOSFET P8 turting on slowly.
The MOSFET N5 and P6 are sized to barely operate correctly in the fast process, temperature and VCC corner. In the slow comer, the current sources I1 and I2 supply additional current drive to ensure proper operation. The voltage rate of change at the gates of the output MOSFETs P7, N7, P8 and N8 is as slow as possible during turn on, while still maintaining conrect operation. The pre-buffer 12 requires the current sources I1 and I2 to vary with temperature and supply variations. The current sources I1 and I2 are made temperature and supply dependent to enable the pre-buffer section 12 to operate correctly. The temperature and supply dependencies are implemented to ensure a slow enough turn on of the output MOSFETs P7 and N8, while still ensuring operation in the slow comer.
Conventional pre-buffers are very difficult to design and optimize. Likewise, conventional pre-buffers require significant updating with each new process version. Additionally, if an inverting scheme is to be implemented, then accurate matching of P and N channel MOSFETs is required for accurate skew and duty cycle performance. Furthermore, the accurate matching of P and N channel MOSFETs is not practical.
Controlling ground/power bounce at high frequencies is a substantial problem common to all higher frequency integrated circuits (IC""s). The present invention provides a control voltage generator coupled to a pre-buffer which is coupled to an output driver. Together these three functional groups allow a single control voltage generator to be utilized even where multiple outputs are required.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a high speed, low skew, low voltage (e.g., transistor-transistor logic (TTL)) output buffer with optional inverting capability that may (i) provide a charge to discharge of an output device that may be less process dependent, (ii) provide current sources that may be derived from a single bandgap source (e.g., allowing slow charge and discharge times to be better matched), (ii) allow the current sources to be derived by forcing an internally generated bandgap voltage across an external resistor to generate current sources that may not be dependent on a process absolute resistor value, (iv) allow the current sources to be VCC, process and temperature dependent to further reduce signal variation, (v) provide a well controlled duty cycle for an inverted implementation, (vi) provide controlled ramp rates and voltage levels allowing for slew control and output ON resistance control, (vii) provide low skew, and/or (viii) reduce ringing and power/ground bounce.